In most synchronous transmission systems, multiplexing technology is widely employed to accommodate as many data channels as possible in a given path. According to a synchronous digital hierarchy (SDH) recommended by the International Standards Union-Telecommunications Sector, digital signal level 1 (DS-1) data or digital signal level 1 of Europe (DS-1E) data is multiplexed to form synchronous transport module level N (STM-N) data through the use of various data packets of containers, virtual containers (VC's), tributary units, and administrative units, wherein the DS-1 and the DS-1E data represent 1.544 Mbps pulse code modulated (PCM) serial data having 24 voice channels and 2.048 Mbps PCM serial data containing 32 voice channels, respectively.
Among the steps of generating the STM-1 from the DS data (DS-1 data or DS-1E data), the present invention relates to a mapping process of the DS data in data packets, e.g., VC's (VC-11's or VC-12's), wherein the VC-11 and the VC-12 are made of the DS-1 and the DS-1E data, respectively.
Conventionally, mapping methods of received data in sending data are classified into an asynchronous mapping, a bit synchronous mapping and a byte-synchronous mapping.
In the synchronous mapping, the clock of received data is matched with that of the sending data. On the other hand, in the asynchronous mapping, the clock frequency of the received data is different from that of the sending data.
In the asynchronous mapping, since the clock frequency of received data is different from that of the sending data, i.e., the clock frequency of the sending data is faster than that of the received data, bit stuffing or gapping of the clock frequency is required to prevent transmission errors.
Referring to FIG. 1A, there is shown a structural diagram of the VC-11. The VC-11 contains 4 frames in 500 .mu.s, and each frame in 125 .mu.s is composed of 2 information bytes and 24 data bytes. The respective information bytes of the first to fourth frame include a low path overhead (V5) byte and eight bits of R, R, R, R, R, R, I and R; a J2 byte and a Y1 byte having C1, C2, 0, 0, 0, 0, I and R; a Z6 byte and a Y2 byte of C1, C2, 0, 0, 0, 0, I and R; a Z7 byte and a Y3 byte having C1, C2, R, R, R, S1, S2 and R. As used herein, R represents a fixed stuffing bit; I, a data bit; C1 and C2, justification control bits; S1 and S2, specification opportunity bits; 0, a supplementary bit; and J2, Z6 and Z7 bytes are reserved bytes for other applications. As is well known in the art, among the information bytes, the V5, the J2, the Z6 and the Z7 bytes, the R, the C1, the C2, and 0 bits are overhead data; and three I bits and four 24 data bytes are payload data coming from the DS data. The S1 or the S2 bit may present overhead data or payload data depending on the C1 and the C2 bits.
Referring to FIG. 1B, there is depicted a structural diagram of the VC-12. The VC-12 also contains 4 frames in 500 .mu.s. The respective information bytes of the first to third frame include a low path overhead (V5) byte and two R* bytes; a J2 byte, a Y1 byte having C1, C2, 0, 0, 0, 0, R and R and a R* byte; a Z6 byte, a Y2 byte of C1, C2, 0, 0, 0, 0, R and R and a R* byte. The information bytes of the fourth frame includes a Z7 byte, a Y3 byte having C1, C2, R, R, R, R, R and S1 and a R* byte. And an S2 bit in the fourth frame is a information bit. As used herein, R represents a fixed stuffing bit; C1 and C2, justification control bits; S1 and S2, specification opportunity bits; 0, a supplementary bit; R* byte, a fixed stuffing byte; and J2, Z6 and Z7 bytes are reserved bytes for other applications. Among the information bytes, the V5, the R*, the J2, the Z6 and the Z7 bytes, the R, the C1, the C2 are overhead data; and three 32 bytes of the first to third frame, and 32 bytes--1 bit of the fourth frame are payload data coming from the DS data. The S1 or the S2 bit may present overhead data or payload data depending on the C1 and the C2 bits.
Referring to FIG. 2, there is illustrated a block diagram of a conventional apparatus 100 for mapping the DS data in the VC's. The mapping apparatus 100 comprises a write address generator 210, a buffer 220, a read address generator 230, an overhead gapping device 240 and a control signal generator 250.
The DS data and a DS clock from a primary multiplexer (not shown), a VC clock and a V5 clock from a VC clock generator (not shown) and a first control signal representing the C1 bit from a stuffing controller (not shown) are inputted to the apparatus 100.
The DS data is inputted to the buffer 220 and the DS clock is provided to the write address generator 210. The write address generator 210, a binary counter, provides a write address for each bit of the DS data and a most significant bit of the write address (WADDMSB) to the buffer 220 and the control signal generator 250, respectively, based on the DS clock. The buffer 220 stores the DS data in the area designated by the write addresses.
Most significant bits of read addresses (RADDMSB's) generated from the read address generator 230 via a line L231, WADDMSB's on a line L211 and the V5 clock are provided to the control signal generator 250. The control signal generator 250 has two D flip-flop (D F/F) circuits, wherein a first D F/F latches a WADDMSB at the changeover of the RADDMSB's from a first logic level, e.g., 1, to a second logic level, e.g., 0, thereof and a second D F/F latches the output of the first D F/F at the onset of the V5 clock. The V5 clock is an initiation signal representing the beginning of a VC. The output from the control signal generator 250 is provided to the overhead gapping device 240 as a second control signal representing the C2 bit. In other words, the C2 bit for a current VC corresponds to a WADDMSB of a previous VC latched from the control signal generator 250 at the onset of the V5 clock for the current VC.
The overhead gapping device 240 gaps clock pulses of the VC clock in response to the V5 clock and the first and the second control signals, i.e., C1 and C2 bits. Specially, the overhead gapping device 240 starts, in response to the V5 clock, gapping clock pulses of the VC corresponding to the V5, J2, Z6 and Z7 bytes, R bits, C1 and C2 bits and zero bits included in the information bytes shown in FIG. 1. Gapping of the S1 and the S2 bits in the information bytes is carried out based on the C1 and C2 bits. For instance, the respective clock pulses corresponding to the S1 and S2 bits are gapped only when the C1 and the C2 bits are zero valued, or vice versa. As is well known, the C1 bit is fixedly determined to 1 for a VC at a rate of 3 by 5 VC's and 0 at a rate of 2 to 5 VC's. For instance, C1 bits are assigned as "1, 0, 1, 0, 1" for each set of 5 consecutive VC's.
The gapped VC clock is then fed to the read address generator 230, which generates a read address for each ungapped clock pulses of the gapped VC clock. The read addresses and most significant bits thereof (RADDMSB's) are provided to the buffer 220 and the control signal generator 250, respectively. At the buffer 220, the stored DS data is retrieved in accordance with the read address and transmitted to an overhead adder (not shown), wherein the overhead data is inserted to the retrieved data from the buffer 220 at the corresponding portion of the gapped VC clock pulses, thereby providing a VC.
Referring to FIG. 3, there is depicted a timing chart illustrating the operation of the apparatus 100 shown in FIG. 2.
The DS clock, e.g., DS1 clock of 1.544 Mbps, is shown on the first line, and the write addresses generated from the write address generator 210 are also illustrated on the second line. The third line is the V5 clock initiating the formation of a VC. The VC clock, e.g., VC-11 clock of 1.664 Mbps, is shown on the fourth line and the fifth line illustrates the output of the overhead gapping device 240 wherein the VC clock is gapped with pulse intervals allocated to the overhead data. The sixth line depicts read addresses obtained by using the gapped VC clock.
In the prior art gapping apparatus, however, gapping of the VC clock is carried out by gapping consecutive clock pulses therein which corresponds to the overhead data, as shown in FIG. 3; and, therefore, the duration of the gapped portion of the VC clock becomes much longer than the VC clock period, which tends to generate a jitter in the gapped VC clock and retrieved data from the buffer 220.